1. Field of the Invention
The invention relates to the fabrication of semiconductor devices, and in particular to a method of fabrication of dielectrically isolated CMOS devices.
2. Description of the Prior Art
Complementary MOS (CMOS) integrated circuits, and their method of fabrication, are well known in the art of semiconductor device technology. One type of CMOS device is implemented on bulk silicon. Complementary MOS integrated circuit on bulk silicon require that the N and P channel devices be electrically isolated from each other. The prior art technique for accomplishing this electrical isolation by junction isolation of either device.
There are significant disadvantages to the junction isolation technique of the prior art. The isolation junction creates parasitic bipolar transistors which in combination form silicon controlled rectifiers (SCR). These devices trigger to the "on" state condition when noise pulses, ionizing radiation, or adverse thermal conditions upset the normal voltage bias operating range for normal IC operation. Once triggered, the circuit "latches up" and recovery can only be obtained by removing power to the device. Prior to the present invention, there has been no effective technique to prevent the latch up condition in CMOS bulk devices when the devices are placed in close proximity.
RCA Technical Note 876, dated Feb. 12, 1971, published by RCA Corporation, Princeton, N.J., apparently describes the use of an N-epitaxial layer on a N+ substrate, in conjunction with guard rings to eliminate parasitic SCR transistors and latching.
U.S. Pat. No. 4,203,126 (Yim et al) approaches the latching problem by a buried layer along with an epitaxial N- layer on an N substrate and guard rings, to affect circuit parameters thus to reduce the gain of the parasitic components.
Dielectric insulated regions are used about MOS devices for isolation in U.S. Pat. No. 4,053,926 (Burr et al).
The combination of an N epitaxial layer on an N+ layer with silicon dioxide thermally grown or deposited in grooves for isolation of integrated circuits is disclosed in U.S. Pat. No. 3,966,577 (Hochberg).